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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Document order number: MC33880/D Rev 1, 09/2002
Advance Information
Configurable Octal Serial Switch with Serial Peripheral Interface I/O
The 33880 device is an eight output hardware configurable high side/low side switch with 8-bit serial input control. Two of the outputs may be controlled directly via microprocessor for PWM applications. The 33880 incorporates SMARTMOSTM technology, with CMOS logic, bipolar/MOS analog circuitry, and DMOS power MOSFETs. The 33880 controls various inductive or incandescent loads by directly interfacing with a micro controller. The circuit's innovative monitoring and protection features include: very low standby currents; cascade fault reporting; internal +40 V clamp voltage for low side configuration; -20 V high side configuration; output specific diagnostics; and independent shutdown of output. Features * Designed to operate 5.5 V < VPWR < 24.5 V * 8-Bit SPI for Control and Fault Reporting, 3.3 V/5.0 V Compatible * Outputs are current limited (0.8 A to 2 A) to Drive Incandescent Lamps * Output voltage Clamp, +45 V (low side) and -20 V (high side) During Inductive Switching * Internal Reverse Battery Protection on VPWR * Loss of Ground or Supply Will Not Energize Loads or Damage IC * Maximum 5 A IPWR Standby Current at 13.0 V VPWR * RDS(ON) of 0.55 at 25C Typical * Short Circuit Detect and Current Limit with Automatic Retry * Independent Over Temperature Protection
Device PC33880DW PC33880DWB 28-Lead SOIC Case751F
33880
CONFIGURABLE OCTAL SERIAL SWITCH WITH SERIAL PERIPHERAL INTERFACE
Package Options
32-Lead Fine Pitch SOIC CASE 1324
ORDERING INFORMATION
Temperature Range (TA) -40C to 125C -40C to 125C Package 28 Ld SOIC 32 Ld SOIC
33880 Simplified Application Schematic
+5.0V VPWR VBAT
MCU
VPWR A0 VDD EN
33880
D1 D2 D3 D4 S1 S2 S3 S4
High Side Drive
MOSI SCLK CS MISO
DI SCLK CS DO
M
PWM1 PWM2 IN5 IN6 D5 D6 D7 D8 S5 S6 S7 S8
H-Bridge Configuration
VBAT
VBAT
Low Side Drive
GND
This document contains certain information on a new product. Specifications and information herein are subject to change without notice. (c) Motorola, Inc. 2002
VDD
VPWR
~50uA
__ CS SCLK DI DO
SPI & Interface Logic
Internal Bias
Charge Pump
Over Voltage Shutdown/POR Sleep State
GND
OV, POR, SLEEP
EN
~50uA
Typical of all 8 output drivers T- lim
SPI Bit 0
IN5
~50uA
enable
Gate Drive Control
Current Limit
Open Load Detect Current ~650uA
D1 D2 D3 D4 D7 D8
Drain Outputs
SPI Bit 4
IN6
~50uA
IN5
S1
+ Open/Short Comparator _
~1.5V Open/Short Threshold
S2 S3 S4 S7 S8 D5
Source Outputs
T- lim
Open Load Detect Current
D6
Drain Outputs
Gate Drive Control
Current Limit
~650uA
S5
+ Open/Short Comparator _
S6
Source Outputs
~1.5V Open/Short Threshold
Figure 1. 33880 Simplified Block Diagram
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
GND VDD S8 S8 D8 S2 D2 S1 D1 D6 S6 IN6 EN SCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
DO VPWR S7 S7 D7 S4 D4 S3 D3 D5 S5 IN5 CS DI
28 Lead SOIC
PIN FUNCTION DESCRIPTON 28 SOIC
28-Lead SOIC PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 GND VDD S8 S8 D8 S2 D2 S1 D1 D6 S6 IN6 EN SCLK DI CS IN5 S5 D5 D3 S3 D4 Digital ground. Logic supply voltage. Logic supply must be switched off for low current mode (VDD below 3.9 V). Output eight MOSFET source pin. Output eight MOSFET source pin. Output eight MOSFET drain pin. Output two MOSFET source pin. Output two MOSFET drain pin. Output one MOSFET source pin. Output one MOSFET drain pin. Output six MOSFET drain pin. Output six MOSFET source pin. PWM direct control input pin for output 6. IN6 is "OR" with SPI bit. Enable input. Allows control of outputs. Active high. SPI control clock input pin. SPI control data input pin from MCU to the 33880. Logic 1 activates output. SPI control chip select input pin from MCU to the 33880. Logic 0 allows data to be transferred in. PWM direct control input pin for output 5. IN5 is "OR" with SPI bit. Output five MOSFET source pin. Output five MOSFET drain pin. Output three MOSFET drain pin. Output three MOSFET source pin. Output four MOSFET drain pin. PIN NAME DESCRIPTION
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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PIN FUNCTION DESCRIPTON 28 SOIC
28-Lead SOIC PIN 23 24 25 26 27 28 S4 D7 S7 S7 VPWR DO Output four MOSFET source pin. Output seven MOSFET drain pin. Output seven MOSFET source pin. Output seven MOSFET source pin. Power supply pin to the 33880. VPWR has internal reverse battery protection. SPI control data output pin from the 33880 to the MCU. DO= 0 no fault, DO= 1 specific output has fault. PIN NAME DESCRIPTION
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
GND VDD S8 S8 D8 S2 D2 GND GND S1 D1 D6 S6 IN6 EN SCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
DO VPWR S7 S7 D7 S4 D4 GND GND S3 D3 D5 S5 IN5 CS DI
32 Lead SOIC
PIN FUNCTION DESCRIPTON 32 SOIC
SOIC-32 PIN NAME PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 GND VDD S8 S8 D8 S2 D2 GND GND S1 D1 D6 S6 IN6 EN SCLK DI CS IN5 S5 D5 D3 Digital ground. Logic supply voltage. Logic supply must be switched off for low current mode (VDD below 3.9 V). Output eight MOSFET source pin. Output eight MOSFET source pin. Output eight MOSFETdrain pin. Output two MOSFET source pin. Output two MOSFET drain pin. Thermal enhanced ground pin. Thermal enhanced ground pin. Output one MOSFET source pin. Output one MOSFET drain pin. Output six MOSFETdrain pin. Output six MOSFET source pin. PWM direct control input pin for output 6. IN6 is "AND" with SPI bit. Enable input. Allows control of outputs. Active high. SPI control clock input pin. SPI control data input pin from MCU to the 33880. Logic 1 activates output. SPI control chip select input pin from MCU to the 33880. Logic 0 allows data to be transferred in. PWM direct control input pin for output 5. IN5 is "AND" with SPI bit. Output five MOSFET source pin. Output five MOSFET drain pin. Output three MOSFET drain pin. DESCRIPTION
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33880 5
PIN FUNCTION DESCRIPTON 32 SOIC
SOIC-32 PIN NAME PIN 23 24 25 26 27 28 29 30 31 32 S3 GND GND D4 S4 D7 S7 S7 VPWR DO Output three MOSFET source pin. Thermal enhanced ground pin. Thermal enhanced ground pin. Output four MOSFET drain pin. Output four MOSFET source pin. Output seven MOSFET drain pin. Output seven MOSFET source pin. Output seven MOSFET source pin. Power supply pin to the 33880. VPWR has internal reverse battery protection. SPI control data output pin from the 33880 to the MCU. DO= 0 no fault, DO= 1 specific output has fault. DESCRIPTION
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted.
Rating VDD Supply Voltage (Note1) CS, DI, DO, SCLK, IN5, IN6, and EN (Note1) VPWR Supply Voltage (Note1) Drain 1 - 8 (5.0 mA IOUT 0.3 A) (Note2) Source 1 - 8 (5.0 mA IOUT 0.3 A) (Note3) Output Voltage Clamp Low Side Drive (Note4) Output Voltage Clamp High Side Drive (Note4) Output Clamp Energy (Note5) ESD Voltage Human Body Model (Note6) Machine Model (Note7) Storage Temperature Operating Case Temperature Operating Junction Temperature Maximum Junction Temperature Power Dissipation 28-SOIC, Case 751F (Ta = 25C) (Note8) Thermal Resistance, Junction-to-Ambient Plastic Package 28 SOIC, Case 751F Power Dissipation 32-SOIC, Case 1324 (Ta = 25C) (Note8) Thermal Resistance, Junction-to-Ambient, Plastic Package 32SOIC, Case 1324, Thermal Resistance Junction to thermal ground leads. Notes: 1. 2. 3. 4. 5. 6. 7. 8. VESD1 VESD2 TSTG TC TJ -- PD RJA PD RJA RJL 2000 200 -55 to +150 -40 to +125 -40 to +150 -40 to +150 1.3 94 1.7 70 18 V V Symbol VDD -- VPWR -- -- VOC VOC ECLAMP Value -0.3 to 7.0 -0.3 to 7.0 -16 to 50 -18 to 40 -28 to 40 40 to 55 -15 to -25 50 Unit VDC VDC VDC VDC VDC VDC VDC mJ
C C C C
W
C/W
W
C/W
Exceeding these limits may cause malfunction or permanent damage to the device. Configured as Low Side Driver with 300 mA load as current limit. Configured as High Side Driver with 300 mA load as current limit. With outputs OFF and 10 mA of test current for low side drive, 30 mA test current for high side drive. Maximum output clamp energy capability at 150C junction temperature using single non-repetitive pulse method. ESD1 testing is performed in accordance with the Human Body Model (CZap = 100 pF, RZap = 1500 ). ESD2 testing is performed in accordance with the Machine Model (CZap = 200 pF, RZap = 0 ). Maximum power dissipation with no heat sink used.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions of 4.75 V VDD 5.25 V, 9.0 V VPWR 16 V, -40C TC 125C, unless otherwise noted. Typical values, where applicable, reflect the parameter's approximate average value with VPWR = 13 V, TA = 25C
Characteristic Symbol Min Typ Max Unit
Power Input
Supply Voltage Range Fully Operational Supply Current Sleep State Supply Current (VDD and EN 0.5 V) VPWR = 16.0 V Over Voltage Shutdown Over Voltage Shutdown Hysteresis Logic Supply Voltage Logic Supply Current Logic Supply Under Voltage Lockout Threshold Logic Supply Under Voltage Hysteresis VOV VOV(hys) VDD IDD VDD(unvol) VDD(unvol-hys) VPWR(fo) IPWR(on) IPWR(ss) 5.5 -- -- -- 25 0.2 4.75 0.5 3.9 100 -- 8.0 2.0 -- 27 0.8 -- 2.6 4.3 150 24.5 14 5.25 25 30 2.5 5.25 4.0 4.6 300 V V V mA V mV V mA A
Power Output
Drain-to-Source ON Resistance (IOUT = 0.250 A, TJ = 125C) (IOUT = 0.250 A, TJ = 25C) (IOUT = 0.250 A, TJ = -40C) Output Self Limiting Current High Side and Low Side Configurations Output Fault Detect Threshold (Note9)(Note10) Outputs Programmed Off Output Off Open Load Detect Current (Note9) Outputs Programmed OFF Output Clamp Voltage Low Side Drive (ID = 10 mA) Output Clamp Voltage High Side Drive (IS = -30 mA) Output Leakage Current High Side and Low Side Configuration (VDD = 0 V, VDS = 16 V) Over Temperature Shutdown (Note10) Over Temperature Shutdown Hysteresis (Note10) TLIM TLIM(HYST) IOCO VOC(LSD) VOC(HSD) IOUT(LKG) -- 155 5.0 -- -- 10 7.0 185 15 0.30 40 -15 0.55 45 -20 0.9 55 -25 mA V V A VOUTth(F) 1.0 -- 3.0 V IOUT(LIM) RDS (on) -- -- -- 0.8 0.75 0.55 0.45 1.4 1.1 0.85 0.80 2.0 A
C C
Notes: 9. Output Fault Detect Thresholds with outputs programmed OFF. Output fault detect threshold are the same for output open and shorts. 10. This parameter is guaranteed by design, but not production tested.
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions of 4.75 V VDD 5.25 V, 9.0 V VPWR 16 V, -40C TC 125C, unless otherwise noted. Typical values, where applicable, reflect the parameter's approximate average value with VPWR = 13 V, TA = 25C Digital Interface
Input Logic Voltage Thresholds (Note11) IN5, IN6, EN Input Logic Current (IN5,IN6,EN = 0 V) IN5, IN6, EN Pull-Down Current (0.8 V to VDD) SCLK, DI, Tri-state DO Input (0 V to VDD) CS Input Current (CS = VDD) CS Pull-Up Current (CS = 0 V) DO High State Output Voltage (IDO-HIGH = -200 A) DO Low State Output Voltage (IDO-HIGH = 1.6 mA) Input Capacitance on SCLK, DI, Tri-state DO, IN5, IN6, EN (Note12) VINLOGIC IIIN5,IN6,EN IIIN5,IN6,EN ISCK,SI,TriSO IICS IICS VDOHIGH VDOLOW CIN 0.8 -10 30 -10 -10 -30 VDD - 0.8 -- -- -- -- 45 -- -- -- -- -- -- 2.2 10 100 10 10 -100 VDD 0.4 20 V A A A A A V V pF
Notes: 11. Upper and lower logic threshold voltage levels apply to DI, CS, SCLK, IN5, IN6, EN. 12. This parameter is guaranteed by design, but not production tested.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33880 9
DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions of 4.75 V VDD 5.25 V, 9.0 V VPWR 16 V, -40C TC 125C, unless otherwise noted. Typical values, where applicable, reflect the parameter's approximate average value with VPWR = 13 V, TA = 25C
Characteristic Symbol Min Typ Max Units
Power Output Timing
Output Rise Time Low Side Configuration (RL = 620) (Note13) Output Fall Time Low Side Configuration (RL = 620 ) (Note13) Output Rise Time High Side Configuration (RL = 620) (Note13) Output Fall Time High Side Configuration (RL = 620 ) (Note13) Output Turn ON Delay Time, High Side and Low Side Configuration (Note14) Output Turn OFF Delay Time, High Side and Low Side Configuration (Note14) Output Fault Delay Time (Note15) tFAULT 100 -- 300 s tDLY(off) 1.0 30 100 s tR tF tR tF tDLY(on) 0.1 0.1 0.1 0.1 1.0 0.5 0.5 0.3 0.3 15 1.0 1.0 1.0 1.0 50 V/s V/s V/s V/s s
Notes:: 13. Output Rise and Fall time respectively measured across a 620 resistive load at 10 to 90 percent and 90 to 10percent voltage points. 14. Output turn ON and OFF delay time measured from 50 percent rising edge of CS to 90 and 10 percent of initial voltage. 15. Duration of fault before fault bit is set. Duration between access times must be greater than 300 S to read faults.
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions of 4.75 V VDD 5.25 V, 9.0 V VPWR 16 V, -40C TC 125C, unless otherwise noted. Typical values, where applicable, reflect the parameter's approximate average value with VPWR = 13 V, TA = 25C
Characteristic Symbol Min Typ Max Units
Digital Interface Timing
Recommended Frequency of SPI Operation Required Low State Duration on VDD for Reset (VDD 0.2 V) (Note16) Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) DI to Falling Edge of SCLK (Required Setup Time) Falling Edge of SCLK to DI (Required Hold Time) DI, CS, SCLK Signal Rise Time (Note17) DI, CS, SCLK Signal Fall Time (Note17) Time from Falling Edge of CS to DO Low Impedance (Note18) Time from Rising Edge of CS to DO High Impedance (Note19) Time from Rising Edge of SCLK to DO Data Valid (Note20) Notes: 16. 17. 18. 19. 20. tRESET tLEAD tLAG tDI(su) tDI(HOLD) tr(DI) tf(DI) tDO(EN) tDO(DIS) tVALID -- -- 100 50 16 20 -- -- -- -- -- 4.0 4.0 -- -- -- -- 5 5 -- -- 25 6.0 10 -- -- -- -- -- -- 55 55 55 MHz s ns ns ns ns ns ns ns ns ns
This parameter is guaranteed by design, but not production tested. Rise and Fall time of incoming DI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. Time required for output status data to be available for use at DO pin. Time required for output status data to be terminated at DO pin Time required to obtain valid data out from DO following the rise of SCLK.
CS
0.2 VDD
tlead
tlag
SCLK
0.7 VDD 0.2 VDD
tDI(su)
tDI(hold)
DI
0.7 VDD 0.2 VDD
MSB in
tDO(en)
tvalid
tDO(dis)
DO
0.7 VDD 0.2 VDD
MSB out
LSB out
Figure 2. SPI Timing Diagram
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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VDD = 5.0 V
SCLK
tr(DI) 0.7 VDD (2.5 V)
< 50 ns 50%
tf(DI)
< 50 ns 5.0 V 0.2 VDD
SCLK
33880 Under Test
0
DO CL = 200 pF
DO (Low-to-High) tdly(lh) 0.2 VDD tvalid 0.7 VDD tdly(hl) 0.2 VDD tr(DO) 0.7 VDD VOH
VOL VOH
NOTE: CL represents the total capacitance of the test
DO (High-to-Low)
VOL
Figure 3. Valid Data Delay Time and Valid Time Test Circuit
Figure 6. Valid Data Delay Time and Valid Time Waveforms
tr(DI)
VDD = 5.0 V
VPull-Up = 2.5 V
CS
<50 ns 90% 10% tDO(en)
tf(DI)
<50 ns 0.7 VDD 5.0 V 0 tDO(dis) VTri-State
CS
33880 Under Test
RL = 1.0 k DO CL = 200 pF
0.2 VDD (2.5 V) DO (Tri-State to Low)
90% 10% tDO(en) tDO(dis) 90% VOH VTri-State tSO(dis)
NOTE: CL represents the total capacitance of the test fixture and probe.
DO (Tri-State to High) 10%
Figure 4. Enable and Disable Time Test Circuit
Figure 7. Enable and Disable Time Waveforms
tr(DI) < 50 ns VDD = 5.0 V VPWR = 13 V CS 0.2 VDD (2.5 V) 90% 10% tDO(en) DO (Tri-State to Low) 90%
tf(DI)
<50 ns 0.7 VDD 5.0 V 0 tDO(dis) VTri-State
CS
33880 Under Test
RL = 620 Output CL
10% tDO(en) NOTE: CL represents the total capacitance of the test fixture and probe. DO (Tri-State to High) 10% 90% tDO(dis)
tSO(dis) VOH
VTri-State
Figure 5. Switching Time Test Circuit
Figure 8. Turn-ON/OFF Waveforms
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
SPI Definition
On each SPI communication, an 8-bit command word is sent to the 33880 and 8-bit fault word is received from the 33880. The MSB is sent and received first Command Register Definition: 0 = Output Commanded OFF 1 = Output Commanded ON Fault Register Definition: 0 = No Fault at Output 1 = Output Short to Bat, Short to GND, Open Load, or TLIM
MSB OUT 8 OUT 7 OUT 6 OUT 5 OUT 4 OUT 3 OUT 2
LSB OUT 1
Fault Operation Serial Output (DO) Pin Reports
Over Temperature Over Current Output ON Open Load Fault Output OFF Open Load Fault Fault reported by Serial Output (DO) pin. DO pin reports short to battery/supply or over current condition Not Reported DO pin reports output OFF open load condition
Device Shutdowns
Over Voltage Total device shutdown at VPWR = 25-30 V. Resumes normal operation with proper voltage. All outputs assuming the previous state upon recovery from overvoltage. Over Temperature Only the output experiencing an over temperature shuts down. Output assumes previous state upon recovery from over temperature.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33880 13
SYSTEM APPLICATION INFORMATION
CIRCUIT DESCRIPTION Introduction
The 33880 is an eight-output hardware configurable power switch with 8-bit serial control. The 33880 incorporates SMARTMOSTM 5 technology with CMOS logic, bipolar/MOS analog circuitry, and independent double diffused DMOS power output transistors. Many benefits are realized as a direct result of using this mixed technology. A simplified block diagram of the 33880 is shown in Figure 1. The 33880 device uses high efficiency updrain power DMOS output transistors exhibiting low drain to source ON resistance values (RDS(on) <= 0.55 at 25C) and dense CMOS control logic. All outputs have independent voltage clamps to provide fast inductive turn-off and transient protection. Operational bias currents of less than 4mA on VDD and 12 mA on VPWR with any combination of outputs ON are a direct result of using SMARTMOSTM 5 technology. In operation, the 33880 functions as an eight-output serial switch serving as a micro controller (MCU) bus expander and buffer with fault management and fault reporting features. In doing so, the device directly relieves the MCU of the fault management functions. This device directly interfaces to an MCU using a Serial Peripheral Interface (SPI) for control and diagnostic readout. Figure 9 illustrates the basic SPI configuration between an MCU and one 33880. Figure 10 illustrates the Daisy Chain configuration using the 33880. Data from the MCU is clocked daisy chain through each device while the Chip Select (CS) bit is commanded low by the MCU. During each clock cycle output status from the daisy chain, the 33880 is being transferred to the MCU via the Master In Slave Out (MISO) line. On rising edge of CS data stored in the input register is then transferred to the output driver.
SCLK Parallel Port
MC68xx Micro controller with SPI Interface
MISO
CS DO DI
CS SCLK DO DI
CS DO
SCLK DI
33880
33880
33880
8 Outputs
8 Outputs
8 Outputs
MOSI
Figure 10. 33880 SPI System Daisy Chain
MC68HCxx Micro controller
MOSI Shift Register MISO DO DI
33880
Multiple 33880 devices can be controlled in a parallel input fashion using the SPI, see Figure 11. This figure illustrates possible 24 loads being controlled by three dedicated parallel MCU ports used for chip select.
MOSI SCLK
DI SCLK DO CS 8Outputs
Shift Register
MISO
SCLK Receive Buffer Parallel Ports CS To Logic
MC68xx Micro controller SPI
DI SCLK DO CS 8Outputs
A
DI SCLK DO CS 8Outputs
Figure 9. SPI Interface with Microcontroller All inputs are compatible with 5.0 V and 3.3 V CMOS logic levels and incorporate positive logic. Whenever an input is programmed to a logic low state (<0.8 V) the corresponding output will be OFF. Conversely, whenever an input is programmed to a logic high state (>2.2 V), the output being controlled will be ON. Diagnostics are treated in a similar manner. Outputs with a fault will feedback (via DO) to the micro as a logic one while normal operating outputs will provide a logic zero.
Parallel Ports
B C
Figure 11. Parallel Input SPI Control
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
PIN FUNCTIONAL DESCRIPTION
CS Pin
The system MCU selects the 33880 to communicate through the use of the CS pin. Whenever the pin is in a logic low state, data can be transferred from the MCU to the 33880 device and vice versa. Clocked-in data from the MCU is transferred from the 33880 shift register and latched into the power outputs on the rising edge of the CS signal. On the falling edge of the CS signal, output status information is transferred from the power outputs status register into the device's shift register. The falling edge of CS enables the DO output driver. Whenever the CS pin goes to a logic low state, the DO pin output is enabled, thereby allowing information to be transferred from the 33880 to the MCU. To avoid any spurious data, it is essential the high-to-low transition of the CS signal occur only when SCLK is in a logic low state. reported as logic one. Conversely, normal operating outputs with non-faulted loads are reported as logic zero. The first positive transition of SCLK will make output eight status available on DO pin. Each successive positive clock will make the next output status available. The DI/DO shifting of data follows a first-in-first-out protocol with both input and output words transferring the most significant bit (MSB) first.
EN Pin
The ENABLE pin on the 33880 device either enables or disables the internal charge pump. The enable pin must be high for this device to enhance the gates of the output drivers, perform fault detection, and reporting. Active outputs during a low transition of the EN pin will become active again when the EN transitions high. If this feature is not required, it is recommended the EN pin be connected to VDD.
SCLK Pin
The system clock pin (SCLK) clocks the internal shift registers of the 33880. The serial data input (DI) is latched into the input shift register on the falling edge of the SCLK. The serial data output pin (DO) shifts data out of the shift register on the rising edge of the SCLK signal. False clocking of the shift register must be avoided to guarantee validity of data. It is essential the SCLK pin be in a logic low state whenever chip select pin (CS) makes any transition. For this reason, it is recommended the SCLK pin is commanded to a logic low state when the device is not accessed (CS in logic high state). When the CS is in a logic high state, any signal at the SCLK and DI pin is ignored and the DO is tri-stated (high impedance).
IN5 and IN6 Pins
The IN5 and IN6 pins command inputs allowing outputs five and six to be used in PWM applications. IN5 and IN6 pins are ORed with the SPI communication input. For SPI control of output five and six, the IN5 and IN6 pins should be grounded or held low by the microprocessor. In the same manor, when using the PWM feature the SPI port must command the outputs off. Maximum PWM frequency for each output is 2 kHz.
VDD Pin
The VDD pin supplies logic power to the 33880 device and is used for power-on reset (POR). To achieve low standby current on VPWR supply, power must be removed from the VDD pin. The device will be in reset with all drivers off when VDD is below 3.9 VDC.
DI Pin
This pin is used for serial instruction data input. DI information is latched into the input register on the falling edge of SCLK. A logic high state present on DI will program a specific output on. The specific output will turn on with the rising edge of the CS signal. Conversely, a logic low state present on the DI pin will program the output off. The specific output will turn off with the rising edge of the CS signal. To program the eight outputs of the 33880 device on or off, enter the DI pin beginning with Output 8, followed by Output 7, Output 6, and so on to Output 1. For each falling edge of the SCLK while CS is logic low, a data bit instruction (on or off) is loaded into the shift register per the data bit DI state. Eight bits of entered information fills the shift register. To preserve data integrity, do not transition DI as SCLK transitions from a high to low logic state.
D1 to D8 Pins
The D1 to D8 pins are the open drain outputs of the 33880. For High Side Drive configurations the Drain pins are connected to battery supply. In Low Side Drive configurations the Drain pins are connected to the low side of the load. All outputs may be configured individually as desired. When Low Side Drive is used the 33880 limit the positive transient for inductive loads to 45 V.
S1 to S8 Pins
The S1 to S8 pins are the source outputs of the 33880. For High Side Drive configurations the Source pins are connected directly to the load. In Low Side Drive configurations the Source is connected to ground. All outputs may be configured individually as desired. When High Side drive is used, the 33880 will limit the negative transient for inductive loads to -20 volts.
DO Pin
The serial data output (DO) pin is the output from the shift register. The DO pin remains tri-state until the CS pin goes to a logic low state. All faults on the 33880 device are reported as logic one through the DO data pin. Regardless of the configuration of the driver, open loads, and shorted loads are
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33880 15
Figure 12. Data Transfer Timing
33880 16
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Power Consumption
The 33880 device has been designed with one sleep and one operational mode. In the sleep mode (VDD 2.0 V) the current consumed by VPWR pin is less than 25 A. To place the 33880 in the sleep mode, turn all outputs off, then remove power from VDD and the EN (enable) input pin. Prior to removing power from the device, it is recommended all control inputs from the micro are low. During normal operation, 4 mA will be drawn from the VDD supply and 12 mA from the VPWR supply.
the second byte the MCU sends to the device is the command byte and will be transferred to the outputs with rising edge of CS.
Over Temperature Fault
Over temperature detect and shutdown circuits are specifically incorporated for each individual output. The shutdown following an over temperature condition is independent of the system clock, or any other logic signal. Each independent output shuts down at 155C to 185C. When an output shuts down due to an over temperature fault, no other outputs are affected. The MCU recognizes the fault by a one in the fault status register. After the 33880 device has cooled below the switch point temperature and 15C hysteresis, the output will activate, unless told otherwise by the MCU via SPI to shutdown.
Paralleling of Outputs
Using MOSFETS as output switches allows the connection of any combination of outputs together. R DS(on) of MOSFETs have an inherent positive temperature coefficient providing balanced current sharing between outputs without destructive operation. The device can even be operated with all outputs tied together. This mode of operation may be desirable in the event the application requires lower power dissipation or the added capability of switching higher currents. Performance of parallel operation results in a corresponding decrease in RDS(on) while the outputs OFF open load detect currents and the output current limits increase correspondingly (by a factor of eight if all outputs are paralleled). Paralleling outputs from two or more different IC devices is possible but not recommended.
Over Voltage Fault
An over voltage condition on the VPWR pin will cause the device to shutdown all outputs until the over voltage condition is removed. When the over voltage condition is removed, the outputs will resume their previous state. This device does not detect an over voltage on the VDD pin. The over voltage threshold on the VPWR pin is specified as 25 to 30 V with 1.0 V typical hysteresis. A VPWR over voltage detect is global causing all outputs to be turned OFF.
Fault Logic Operation
Fault logic of the 33880 device has been greatly simplified over other devices using SPI communications. As command word one is being written into the shift register, a fault status word is being simultaneously written out and received by the MCU. Regardless of the configuration, with no outputs faulted, all status bits being received by the MCU will be zero. When outputs are faulted (off state open circuit or on state short circuit/over temperature), the status bits being received by the MCU will be one. The distinction between open circuit fault and short/over temperature is completed via the command word. For example, when a zero command bit is sent and a one fault is received in the following word, the fault is open/short to battery for high side drive or open/short to ground for low side drive. In the same manor when a one command bit is sent and a one fault is received in the following word the fault is a short to ground/over temperature for high side drive or short to battery/over temperature for low side drive. The timing between two write words must be greater than 300 S to allow adequate time to sense and report the proper fault status.
Output OFF Open Load Fault
An output OFF open load fault is the detection and reporting of an open load when the corresponding output is disabled (input bit programmed to a logic low state). The output OFF open load fault is detected by comparing the drain-to-source voltage of the specific MOSFET output to an internally generated reference. Each output has one dedicated comparator for this purpose. An output off open load fault is indicated when the drain-tosource voltage is less than the output threshold voltage (VTHRES) of 1.0 to 3.0 V. Hence, the 33880 will declare the load open in the OFF state when the VDS is less than 1.0 V. This device has an internal 650 A current source connected from drain to source of the output mosfet. This prevents either configuration of the driver from having a floating output. To achieve low sleep mode quiescent currents, the open load detect current source of each driver are switched off when VDD is removed. During output switching, especially with capacitive loads, a false output OFF open load fault may be triggered. To prevent this false fault from being reported, an internal fault filter of 100 to 300 S is incorporated. A false fault reporting is a function of the load impedance, RDS(ON), COUT of the MOSFET as well as the supply voltage, VPWR. The rising edge of CS triggers the built-in fault delay timer. The timer will time out before the fault comparator is enabled and the fault is detected. Once the
SPI Integrity Check
It is recommended to check the integrity of the SPI communication with the initial power-up of the VDD and EN pins. After initial system start-up or reset, the MCU will write one, 16 bit pattern to the 33880. The first eight bits read by the MCU will be the fault status of the outputs while the second eight bits will be the first byte of the bit pattern. By the MCU receiving the same bit pattern it sent, bus integrity is confirmed. Please note
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33880 17
condition causing the open load fault is removed, the device will resume normal operation. The open load fault however, will be latched in the output DO register for the MCU to read.
Drain-to-Source Clamp Voltage (VCL = 40 V)
Drain Voltage
Shorted Load Fault
A shorted load (over current) fault can be caused by any output being shorted directly to supply, or an output experiencing a current greater than the current limit. There are two safety circuits progressively in operation during load short conditions providing system protection. 1. The device's output current is monitored in an analog fashion using SENSEFETTM approach and current limited. 2. The device's output thermal limit is sensed and when attained causes only the specific faulted output to shutdown. The output will remain off until cooled. The device will then reassert the output automatically. The cycle will continue until fault is remove or the command bit instructs the output off.
Drain Current (ID = 0.3 A)
Clamp Energy (EJ = IA x VCL)
Drain-to-Source ON Voltage (VDS(ON))
GND
Drain-to-Source ON Voltage (VDS(ON)) VS
Current Area (IA)
Time BAT
GND
Current Area (IA)
Time
Clamp Energy (EJ = IA x VCL) Source Current
Under Voltage Shutdown
An under voltage VDD condition will result in the global shutdown of all outputs. The undervoltage threshold is between 3.9 V and 4.6 V. When VDD goes below the threshold, all outputs are turned OFF and the Fault Status (FS) register is cleared. As VDD returns to normal levels, the FS register will resume normal operation. An under voltage condition at the VPWR pin will not cause output shutdown and reset. When VPWR is between 5.5 V and 9.0 V, the output will operate per the command word. However, the status as reported by the serial data output (DO) pin may not be accurate below 9.0 V VPWR. Proper operation at VPWR voltages below 5.5 V can not be guaranteed.
(IS = 0.3 A) Source Clamp Voltage (VCL = -20 V)
Source Voltage
Figure 13. Output Voltage Clamping
SPI Configurations
The SPI configuration on the 33880 device is consistent with other devices in the OSS family. This device may be used in serial SPI or parallel SPI with the 33298 and 33291. Different SPI configurations may be provided. For more information, contact Motorola SMARTMOSTM Analog Products Division or local Motorola representative.
Reverse Battery
The 33880 has been designed with reverse battery protection on VPWR pin. However, the device does not protect the load from reverse battery. During the reverse battery condition, current will flow through the load and the output MOSFET substrate diode. Under this circumstance, relays may energize and lamps will turn on. No damage will occur to the 33880. If load reverse battery protection is desired a diode must be placed in series with the load.
Output Voltage Clamp
Each output of the 33880 incorporates an internal voltage clamp to provide fast turn-off and transient protection of each output. Each clamp independently limits the drain-to-source voltage to 45 V for low side drive configurations and -20 V for high side drive configurations. The total energy clamped (EJ) can be calculated by multiplying the current area under the current curve (IA) times the clamp voltage (VCL). Characterization of the output clamps, using a single pulse non-repetitive method at 0.3 A, indicate the maximum energy to be 50 mJ at 150C junction temperature per output.
33880 18
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
TYPICAL ELECTRICAL CHARACTERISTICS
IPWR Current into VPWR Pin (mA)
14
VPWR @ 16V
1.4
VPWR @ 16V
12 RDS(ON) () 25 50 75 100 125 10 8 6 4 2 -40 -25 0
All Outputs OFF All Outputs ON
1.2 1.0 0.8 0.6 0.4 0.2 -40 -25 0 25 50 75 100 125
TA, Ambient Temperature (C) Figure 14. IPWR vs. Temperature Sleep State IPWR versus Temperature IPWR Current into VPWR Pin (uA) (A) 14
VPWR @ 16V
TA, Ambient Temperature (C) Figure 17. RDS(ON) vs. Temperature@250 mA 1.4 1.2 RDS(ON) () 1.0 0.8 0.6 0.4 0.2
VPWR @ 16V
12 10 8 6 4 2 -40 -25 0 0 25 50 75 100 100 125 125
0
5
10
15
20
25
TA, Ambient Temperature (C) Figure 15. Sleep State IPWR vs. Temperature IPWR Current into VPWR Pin (A) 14
TA = 25C
VPWR (V) Figure 18. RDS(ON) vs. VPWR @ 250 mA 1.6
VPWR @ 16V
12 10 8 6 4 2 0 5 10 VPWR Figure 16. Sleep State IPWR vs. VPWR 15 20 25 IOUT(LIM), Current Limit (A)
1.5 1.4 1.3 1.2 1.1 1.0 -40 -25 0 25 50 75 100 125
TA, Ambient Temperature (C) Figure 19. Current Limit IOUT(LIM) vs. Temperature
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33880 19
TYPICAL ELECTRICAL CHARACTERISTICS
1.4 IOCO, Open Load (mA) IOCO Open Load (mA) 1.2 1.0 0.8 0.6 0.4 0.2 -40 -25 0 25 50 75 100 125
VPWR @ 16V High Side Configuration
1.4
TA = 25C
1.2 1.0 0.8 0.6 0.4 0.2 0 5 10 15 20 25
TA, Ambient Temperature (C) Figure 20. Open Load Detect Current vs. Temperature
VPWR (V) Figure 21. Open Load Detect Current vs. VPWR
IOUT(LKG), Leakage Current (A)
1.4
TA = 25C
1.2 1.0 0.8 0.6 0.4 0.2 0 5 10 15 20 25
VPWR (V) Figure 22. Sleep State Output Leakage vs. VPWR
33880 20
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
PACKAGE DIMENSIONS
A D
28 15 M NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 4. MAXIMUM MOLD PROTRUSION 0.015 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION.
1
14 PIN 1 IDENT
B
0.25 M
E
H
B
Millimeters DIM Min. A 2.35 0.13 0.35 0.23 17.80 7.40 10.05 0.41 0 Max 2.65 0.29 0.49 0.32 18.05 7.60 10.55 0.90 8
A
L 0.10 C C
SEATING PLANE
A1 B C D
e B 0.025
M
A1
q
CA
S
B
E e H L
S
1.27 BSC
Figure 23. Case 751F
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33880 21
PACKAGE DIMENSIONS
DWB SUFFIX (32-LEAD SOIC) PLASTIC PACKAGE CASE 1324 ISSUE A
10.3 7.6 7.4 C 5
1 32
B 9
2.65 2.35
30X
0.65
PIN 1 ID 4 B 9 11.1 10.9 C L
16
17
5.15
2X 16 TIPS
A
32X
SEATING PLANE
0.3 A B C A (0.29) 0.25 0.19 A 6 0.13
M BASE METAL
0.10 A
NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. DATUMS B AND C TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 5. THIS DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 6. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.4 MM PER SIDE. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD SHALL NOT LESS THAN 0.07 MM. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 MM AND 0.3 MM FROM THE LEAD TIP. 9. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. THIS DIMENSION IS DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTER-LEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY.
(0.203) 0.38 0.22 CA
M
R0.08 MIN 0.25
GAUGE PLANE
0
MIN
PLATING
0.29 0.13
B
8 8 0 0.9 0.5 SECTION B-B
ROTATED 90 CLOCKWISE
SECTION A-A
Figure 24. Case 1324
33880 22
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
NOTES:
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33880 23
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